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Z86C27/C97 CPS DC-2974-04
CUSTOMER PRODUCT SPECIFICATION
Z86C27-ROM Z86C97-ROMLESS
CMOS Z8(R) 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The Z86C27 and Z86C97 Digital Television Controller (DTC) introduce a new level of sophistication to single-chip architecture. The Z86C27/C97 are members of the Z8 single-chip microcontroller family with 8 Kbytes of ROM (Z86C27), ROMless (Z86C97) and 236 bytes of RAM. Both devices are housed in a 64-pin DIP package, and are CMOS compatible. Having the ROM/ROMless selectivity, the DTC offers both external memory and pre-programmed ROM which enables the Z8 microcontroller to be used in a high volume production application device embedded with a custom program (customer supplied program). The Z86C97 ROMless offers the use of external memory rather than a preprogrammed ROM. This enables the Z8 microcontroller to be used in prototyping, low volume applications or where code flexibility is required. Zilog's DTC offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. The device provides an ideal performance and reliability solution for consumer and industrial television applications. The Z86C27/C97 architecture is characterized by utilizing Zilog's advanced SuperintegrationTM design methodology. The devices have an 8-bit internal data path controlled by a Z8 microcontroller, and On Screen Display (OSD) logic circuits/Pulse Width Modulators (PWM). Onchip peripherals include two register mapped I/O ports (Ports 2 and Port 3), Interrupt control logic (1 software, 2 external and 3 internal interrupts) and a standby mode recovery input port (Port 3, pin P30). The OSD control circuits support 8 rows by 20 columns for 128 kinds of characters. The character color is specified by row. One of the 8 rows is assigned to show two kinds of colors for bar type displays such as volume control. The OSD is capable of displaying either low resolution (5x7 dot pattern) or high resolution (11x15 dot pattern) characters. The Z86C97 currently supports high resolution characters only. A 14-bit PWM port provides enough voltage resolution for a voltage synthesizer tuning system. Seven 6-bit PWM ports are used for controlling audio signal level. Five 8-bit PWM ports are used to vary picture levels. The DTC applications demand powerful I/O capabilities. The Z86C27/C97 fulfills this with 35 I/O pins dedicated to input and output. These lines are grouped into five ports, and are configurable under software control to provide timing, status signals, parallel I/O and an address/data bus for interfacing to external memory. There are three basic address spaces available to support this wide range of configurations: Program Memory, Register File and Data Memory. The Register File is composed of 236 bytes of general purpose register, two I/O Port registers and 15 control and status registers. To unburden the program from coping with the real-time problems such as counting/timing and data communication, the DTC's offer two on-chip counter/timers with a large number of user selectable modes (see block diagram). Note: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only).
DC-2974-04
(6-10-93)
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Z86C27/C97 CPS DC-2974-04
GENERAL DESCRIPTION (Continued)
XTAL1 XTAL2 /RESET RESET Oscillator WDT Counter Timer Counter Timer P30 P31 P34 P35 P36 P40( P10 ) P41( P11 ) P42( P12 ) P43( P13 ) P44( P14 ) P45( P15 ) P46( P16 ) P47( P17 ) P50( P00 ) P51( P01 ) P52( P02 ) P53( P03 ) P54( P04 ) P55( P05 ) P56( P06 ) P57( P07 ) P60( /AS ) P61( /DS ) P62( R//W ) P63( SCLK ) P64( P66 )* P65( P67 )* AFCIN Port 3/ Interrupt 256 Byte Register File PWM 1 14 -bit PWM 1 PWM 2 PWM 3 PWM 4 PWM 5 PWM 6 PWM 7 PWM 8 PWM 9 PWM 10 PWM 11 PWM 12 PWM 13 8K Byte Program ROM Port 2 Z8 CPU Core P27 P26 P25 P24 P23 P22 P21 P20
Port4 (Port 1)
Port 0 A8:15
Port 1 AD0:7
PWM 2 to PWM 8 6-bit
Port 5 (Port 0)
PWM 9 to PWM 13 8-bit
160 Byte Character RAM Port 6 (Control) 4 KByte Character ROM
On Screen Display
OSCIN OSCOUT HSYNC VSYNC VRED VGREEN VBLUE VBLANK
* ( ) Denotes Z86C97 signal differences.
Functional Block Diagram
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Z86C27/C97 CPS DC-2974-04
PIN CONFIGURATION
PWM5 PWM4 PWM3 PWM2 PWM1 P35 P36 P34 P31 P30 XTAL1 XTAL2 /RESET P60 GND P61 P62 VCC P63 P64 P65 AFCIN P50 P51 P52 P53 P54 P55 P56 P57 OSCIN OSCOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PWM6 PWM7 PWM8 PWM9 PWM10 PWM11 PWM12 PWM13 P27 P26 P25 P24 P23 GND P22 P21 VCC P20 P47 P46 P45 P44 P43 P42 P41 P40 VBLANK VBLUE VGREEN VRED VSYNC HSYNC
PWM5 PWM4 PWM3 PWM2 PWM1 P35 P36 P34 P31 P30 XTAL1 XTAL2 /RESET /AS GND /DS R//W VCC SCLK P66 P67 AFCIN P00 P01 P02 P03 P04 P05 P06 P07 OSCIN OSCOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 Z86C97 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PWM6 PWM7 PWM8 PWM9 PWM10 PWM11 PWM12 PWM13 P27 P26 P25 P24 P23 GND P22 P21 VCC P20 P17 P16 P15 P14 P13 P12 P11 P10 VBLANK VBLUE VGREEN VRED VSYNC HSYNC
Z86C27
Z86C27 Mask-ROM Plastic DIP
Z86C97 ROMless Plastic DIP
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Z86C27/C97 CPS DC-2974-04
ABSOLUTE MAXIMUM RATINGS
Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Symbol VCC VI VI VO IOH IOH IOL IOL IOL TA TSTG
Parameters Power Supply Voltage Input Voltage Input Voltage Output Voltage Output Current High Output Current High Output Current Low Output Current Low Output Current Low,all total Operating Temperature Storage Temperature
Min -0.3 -0.3 -0.3 -0.3
Max +7 VCC +0.3 VCC +0.3 VCC +8.0 -10 -100 20 40 200
Units V V V V mA mA mA mA mA C
Notes
[1] [2] 1 pin all total 1 pin [3] (1 pin)
-65
+150
Notes: [1] Port 2 open-drain [2] PWM open-drain outputs [3] Port 5
Voltage on all pins with respect to GND. See Ordering Information
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (see Test Load Diagram).
From Output Under Test
VDD
RLL
150 pF
RLH
Test Load Diagram
CAPACITANCE TA=25C, VCC=GND=0 V, Freq=1.0 MHz, unmeasured pins to GND.
Parameter Input capacitance Output capacitance I/O capacitance AFCIN input capacitance Max 10 20 25 10 Units pF pF pF pF
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Z86C27/C97 CPS DC-2974-04
DC CHARACTERISTICS TA=0C to +70C; VCC=+4.5 V to +5.5 V; FOSC=4 MHz
Symbol Parameter VIL VILC VIH VIHC VHY VPU VOL Input Voltage Low Input XTAL/Osc In Low Input Voltage Input XTAL/Osc in High Schmitt Hysteresis Maximum Pull-up Voltage Output Voltage Low TA=0C to +70C Min Max 0 0.7 VCC 0.8 VCC 0.1 VCC 12 0.4 0.4 0.4 1.5 0.45 VCC 0.75 VCC -80 3.0 3.0 20 6 10 0.2 VCC 0.07 VCC VCC VCC Typical @ 25C Units Conditions 1.48 0.98 3.0 3.2 0.8 0.16 0.19 0.19 1.00 1.9 3.12 4.75 -46 0.01 0.02 13.2 3.2 0 V V V V V V V V V V V V V A A A mA mA A External Clock Generator Driven External Clock Generator Driven [2] IOL=1.00 mA IOL=3.2 mA, [1] IOL=0.75 mA [2] IOL=10 mA [1]
V00-01 V01-11 VOH IIR IIL IOL ICC ICC1 ICC2
AFC Level 01 In AFC Level 11 In Output Voltage High Reset Input Current Input Leakage Tri-State Leakage Supply Current
0.5 VCC VCC-0.4 -3.0 -3.0
IOH= -0.75 mA VRL=0 V 0 V,VCC 0 V,VCC All inputs at rail All inputs at rail All inputs at rail
Notes: [1] Port 5 [2] PWM Open-Drain
AC CHARACTERISTICS Timing Diagrams
1
3
7
5
XTAL1
Tin
3 2
2
4 6
External Clock
Counter Timer
5
Z86C27/C97 CPS DC-2974-04
IRQn
8
9
Interrupt Request
Vcc
10
11
Internal /RESET
12
External /RESET
Power On Reset
HSYNC
13
14
OSC2
On Screen Display
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Z86C27/C97 CPS DC-2974-04
AC CHARACTERISTICS TA=0 C to +70 C; VCC=+4.5 V to +5.5 V; FOSC=4 MHz,
No 1 2 3 4 5 6 7 8A 8B 9 10 11 12 13 14 15 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH TdPOR TdLVIRES TwRES TdHsOI TdHsOh TdWDT Parameter Input clock period Clock input raise and fall Input clock width Timer input low width Timer input high width Timer input period Timer input raise and fall Int req input low Int request input high Power On Reset delay Low voltage detect to InInternal RESET condition Reset minimum width Hsync start to Vosc stop Hsync end to Vosc start WDT Refresh Time Min 250 125 70 3 TpC 8 TpC 100 70 3 TpC 3 TpC 25 200 5 TpC 2 TpV ns ns Max 1000 15 Unit ns ns ns ns
100
ms ns
3 TpV 1 TpV 12
ms
Notes: [1] Refer to DC Characteristics for details on switching levels. * Units in nanoseconds
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Z86C27/C97 CPS DC-2974-04
AC CHARACTERISTICS Unique to Z86C97 External Memory Read/Write Timing Diagram
R//W
13 12
Port 0, /DM
16 19 3
Port 1
A7 - A0
1 2
D7 - D0 IN
9
/AS
8 4 5 6 18 11
/DS (Read)
17
10
Port1
A7 - A0
14
D7 - D0 OUT
15 7
/DS (Write)
Z86C97 External Memory Read/Write Timing
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Z86C27/C97 CPS DC-2974-04
AC CHARACTERISTICS Unique to Z86C97, TA=0C to +70C; VCC=+4.5 V to +5.5 V; FOSC = 4 MHz
No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Symbol TdA(AS) TdAS(AS) TdAS(DR) TwAS TdAZ(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDI(DS) Parameter Address Valid to /AS High Delay /AS High to Address Float Delay /AS High to Read Data Required Valid /AS Low Width Address Float to /DS Low /DS (Read) Low Width DS (Write) Low Width /DS Low to Read Data Required Valid Read Data to /DS High Hold /DS High to Address Active Delay /DS High to /AS Low Delay R//W Valid to /AS High Delay /DS High to R//W Not Valid Write Data Valid to /DS Low Delay /DS High to Write Data Not Valid Address Valid to Read Data Required Valid /AS High to /DS Low Delay Data Input Setup to /DS High Min 35 45 250 55 0 185 110 130 5 55 55 35 55 35 55 330 65 75 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes [2] [2] [1,2] [2] [2] [1,2] [1,2] [1,2] [2] [2] [2] [2] [2] [2] [1,2] [2] [1]
Notes: [1] When using extended memory timing, for parameters 3, 6, 7, 8, and 16, add 2 TpC (250 ns @ 4.0 MHz). [2] Min and Max times are in nanoseconds unless otherwise noted.
(c) 1993 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056
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